243 research outputs found

    A Feature Extractor IC for Acoustic Emission Non-destructive Testing

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    In this paper, we present the design and the implementation of a digital Application Specific Integrated Circuit (ASIC) for Acoustic Emission (AE) non-destructive testing. The AE non-destructive testing method is a diagnostic method used to detect faults in mechanically loaded structures and components. If a structure is subjected to mechanical load or stress, the presence of structural discontinuities releases energy in the form of acoustic emissions through the constituting material. The analysis of these acoustic emissions can be used to determine the presence of faults in several structures. The proposed circuit has been designed for IoT (Internet of Things) applications, and it can be used to simplify the existing procedures adopted for structural integrity verifications of pressurized metal tanks that, in some countries, they are based on periodic checks. The proposed ASIC is provided of Digital Signal Processing (DSP) capabilities for the extraction of the main four parameters used in the AE analysis that are the energy of the signal, the duration of the event, the number of the crossing of a certain threshold and finally the maximum value reached by the AE signal. The circuit is provided of an SPI interface capable of sending and receiving data to/from wireless transceivers to share information on the web. The DSP circuit has been coded in VHDL and synthesized in 90 nm technology using Synopsys. The circuit has been characterized in terms of area, speed, and power consumption. Experimental results show that the proposed circuit presents very low power consumption properties and low area requirements

    Lenti oftalmiche in Java 3D

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    L'obiettivo del progetto è quello di proporre uno strumento di visualizzazione 3D di lenti oftalmiche che le appresenti prima della loro effettiva fabbricazione, mettendone in risalto gli spessori. La scelta dell'utilizzo di Java3d ha portato alla realizzazione di un software leggero ma con grafica di qualitàope

    I sistemi informativi nel Nord Africa romano: sicurezza interna e intelligence militare.

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    The need to maintain control over the border areas in North Africa led Rome to set up an information network to keep a close watch on Berber pressure on the borders. Here we will try to outline a framework on the basis of the epigraphic material that has been publishedL’esigenza di mantenere il controllo delle aree limitanee nei territori del Nord Africa portò Roma a mettere in campo una rete informativa tale da poter tenere sotto stretta vigilanza le pressioni berbere sui confini. Si proverà qui a delineare un quadro sulla base del materiale epigrafico edito

    FPGA Implementation of Hand-written Number Recognition Based on CNN

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    Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps.  For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%

    Case-specific parametric analysis as research-directing tool for analysis and design of GFRP-RC structures

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    This paper presents a parametric analysis of the ACI440 (2015) and AASHTO (2009) algorithms governing the flexural design of a one-way concrete member internally reinforced with glass fiber-reinforced polymer (GFRP) bars. The influence of specific design parameters on the required amount of reinforcement is investigated. The aim is to identify variables and requirements governing the design of a large-section GFRP reinforced concrete (RC) member. The member considered for this case-specific analysis is the reinforced concrete pile cap of the Halls River Bridge (Homosassa, FL), which is deemed representative of large-section GFRP-RC members operating as bent caps in short-span bridges. The influence of four critical parameters on the required amount of reinforcement is assessed. Salient analysis and design implications are discussed with respect to creep and fatigue rupture stress limits, minimum amount of flexural reinforcement, and applicable strength reduction factors. The outcomes of the parametric analysis highlight an untapped potential to reduce the required amount of reinforcement, and prioritize research areas to advance the development of rational design algorithms. Cyclic fatigue and creep rupture are identified as governing mechanisms

    multitemporal analysis of algal blooms with meris images in a deep meromictic lake

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    MERIS images (2003-2011) were used to detect algal bloom events in Lake Idro (Northern Italy) applying a semi-empirical algorithm. From the study of an intense phenomenon occurred in late summer 2010, a retrospective analysis of similar events during late summer/ early autumn period was performed. High intra- and inter-annual variability was observed and three additional bloom events were identified on 2003, 2005 and 2008. Hydrological and weather parameters were examined at different temporal intervals (August-October, September-October and monthly from August to October) to investigate the regulating factors of bloom incidence. Rather low temperatures and the persistence of clouds seem t

    A Feature Extractor IC for Acoustic Emission Non-destructive Testing

    Get PDF
    In this paper, we present the design and the implementation of a digital Application Specific Integrated Circuit (ASIC) for Acoustic Emission (AE) non-destructive testing. The AE non-destructive testing method is a diagnostic method used to detect faults in mechanically loaded structures and components. If a structure is subjected to mechanical load or stress, the presence of structural discontinuities releases energy in the form of acoustic emissions through the constituting material. The analysis of these acoustic emissions can be used to determine the presence of faults in several structures. The proposed circuit has been designed for IoT (Internet of Things) applications, and it can be used to simplify the existing procedures adopted for structural integrity verifications of pressurized metal tanks that, in some countries, they are based on periodic checks. The proposed ASIC is provided of Digital Signal Processing (DSP) capabilities for the extraction of the main four parameters used in the AE analysis that are the energy of the signal, the duration of the event, the number of the crossing of a certain threshold and finally the maximum value reached by the AE signal. The circuit is provided of an SPI interface capable of sending and receiving data to/from wireless transceivers to share information on the web. The DSP circuit has been coded in VHDL and synthesized in 90 nm technology using Synopsys. The circuit has been characterized in terms of area, speed, and power consumption. Experimental results show that the proposed circuit presents very low power consumption properties and low area requirements
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